1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and, more specifically, to a nonvolatile semiconductor memory device having a memory cell array arranged with a plurality of memory cells that can store information as a result of changed electrical attributes and erase and program the information by electrically changing the electrical attributes.
2. Description of the Related Art
Recently, flash memories have become mainstream of nonvolatile semiconductor memory devices having a memory cell array arranged with a plurality of memory cells that can electrically erase and program information. The most general flash memories include ETOX (EPROM Thin Oxide, registered trademark of Intel Corporation) type flash memories. FIG. 1 is a view showing an equivalent circuit of a memory cell array of an ETOX type flash memory, and FIG. 2 is a schematic sectional view for illustrating one example of MOSFET included in memory cells and its equivalent circuit. A memory cell array 10 is such configured that it has memory cells 100 arranged in rows and columns like a matrix, a control gate 20 of memory cells 100 on a same row is connected to common word lines WL0 to WLn, a drain 24 of the memory cells 100 on a same column is connected to common bit lines BL0 to BLm, and a source 25 of the memory cells 100 is connected to a common source line SL.
In a MOSFET included in memory cells 100, an oxide film 23 is formed on a channel area 26 between a source 25 and a drain 24, a floating gate 22 as a charge accumulated area is formed on the oxide film 23, an inter-layer insulating film 21 is formed on the floating gate 22, and a control gate 20 is formed on the inter-layer insulating film 21. In the floating gate 22, information is programmed into and erased from the memory cells 100, by injecting and drawing electrons into/from the floating gate 22. In other words, threshold voltage of the memory cells varies, depending on how many electrons exist on the floating gate 22. Thus, for instance, such a condition that the threshold voltage of the memory cells 100 belongs to a distribution range where the threshold voltage becomes higher by injecting electrons into the floating gate 22 shall be referred to as a first condition, on the other hand, such a condition that the threshold voltage of the memory cells 100 belongs to the distribution range where the threshold voltage becomes lower by drawing electrons from the floating gate 22 shall be referred to as a second condition, to distinguish them.
However, the electron drawing speed varies depending on each memory cell 100, as memory cells 100 have such production variation as film thickness or minute defects of an oxide film 23. In fact, even though electrons were drawn in a similar manner, threshold voltage of each memory cell 100 could not be constant. Thus, if the memory cell array 10 includes (n+1)×(m+1) memory cells 100 and thus there can exist more than one memory cell 100 having different threshold voltage, the threshold voltage of the memory cells 100 will have distributions worth of the number of memory cells 100. In fact, when information is erased collectively, and if memory cells with lower electron drawing speed are in the second condition, memory cells with higher electron drawing speed will be out of the second condition. As these memory cells that are out of the second condition may cause various problems, there was need of finally eliminating them.
Thus, a flash memory for which a measure for memory cells being out of the second condition has been taken are now under study. First, memory cells in the second condition are detected and voltage is applied to the memory cells until they are in the first condition. Then, information is erased collectively so that selected memory cells that have been selected to be erased may be in the second condition.
If information is collectively erased as such, there result in memory cells that are out of the second condition due to a difference in the electron drawing speed, as described above. Thus, the memory cells that are out of the second condition should be detected by setting voltage of word lines. Then, information should be programmed back to all the memory cells connected to the bit lines by applying program back voltage to them. In addition, programming back of information could continue until the memory cells that are out of the second condition no longer exist on the bit lines, by making judgment of whether or not there is no memory cell on the bit lines that is out of the second condition.
As such, an attempt is being made to program back information by the memory cell, for the memory cells that are out of the second condition (See, for example, Japanese Laid-Open Patent Publication No. 8-106793).
In addition, FIG. 7 is a flow chart showing the procedure of erasure action in other examples of flash memories for which the measure for the memory cells that are out of the second condition have been taken.
First, memory cells in the second condition are detected and the action of preliminarily programming information to the memory cells is performed until they are in the first condition (ST 71). Next, by using “erasure judgment level 1” that has been set higher than target “erasure judgment level 2”, a first erasure action of information of selected memory cells that have been selected as target cells of erasing is performed (ST 72). Then, the first erasure action continues until it is judged that the threshold voltage of the memory cells is below the “erasure judgment level 1” (hereinafter abbreviated as “first erase-verify action”, as appropriate) (ST 73). Then, the first program-back action is performed (ST 74) until it is judged that the threshold voltage of the memory cells is higher than or equal to “program-back judgment level 1” (hereinafter abbreviated as “first program-back-verify action”, as appropriate) (ST 75). Then, considering that threshold voltage of other memory cells also appears to be low due to effect of memory cells having excessively low threshold voltage, the first program-back-verify action is performed by the “program-back judgment level 1” that has been set lower than the target “program-back judgment level 2”.
Thus, by performing steps ST 72 to ST 75, information is programmed back so that the memory cells having excessively low threshold voltage can have threshold voltage in a certain range. Then, as the first program-back verify action eliminates the memory cells having excessively low threshold voltage, which thus removes the phenomenon that distribution of the threshold voltage throughout the memory cell array looks dropped, distribution of real threshold voltage will be shown.
Next, using the “erasure judgment level 2”, a second erasure action of erasing information of selected memory cells that have been selected to be erased is performed (ST 76). Then, the second erasure action is performed until it is judged that the threshold voltage of the memory cells is below the “erasure judgment level 2” (hereinafter abbreviated as “second erase-verify action”, as appropriate) (ST 77). Then, a second program-back action is performed (ST 78) until it is judged that the threshold voltage of the memory cells is higher than the “program-back judgment level 2” (hereinafter abbreviated as “second program-back-verify action”, as appropriate) (ST 79).
Thus, by performing steps ST 76 to ST 79, information can be programmed back so that the memory cells that do not shift to the second condition can shift to the second condition (See, for example, Japanese Laid-Open Patent Publication No. 2001-184876).
In addition, in ETOX type flash memories, provision of more than two distribution ranges of threshold voltage could make it possible to implement multilevel storage, which is greater than two values, in one memory cell. FIG. 3 schematically shows one example of a distribution range of the threshold voltage of a memory cell in a four-valued flash memory. The horizontal axis represents threshold voltage of memory cells, while the vertical axis represents the number of memory cells. The distribution range of the threshold voltage are partitioned into 4 sections and set, four types of data values “11”, “10”, “01”, “00” are assigned to the distribution ranges in ascending order of the threshold voltage.
Such a method of writing information of multilevel flash memory is disclosed in Japanese Laid-Open Patent Publication No. 9-45094. FIG. 8 is a flow chart showing the operation procedure in collectively writing the four types of data values, depending on content. First, a data value of a selected memory cell that has been selected as a target cell to be erased shall be set to “00”. In fact, information has been programmed back so that threshold voltage of memory cells that fall outside of the distribution range corresponding to the data “00” can belong to the corresponding distribution range.
Then, a write data generating unit generates multilevel data “00”, “01”, “10”, and “11” to be written into respective memory cells, and writes them into a bit line register (ST 81).
Next, i=1 is set in an index counter (ST 82), and the data “11” is outputted from the write data generating unit (ST 83). The outputted data “11” is sequentially compared with contents of respective registers (“00” “01”, “10”, or “11”). When registers that store the same data value as the data “11” are found, flags corresponding to these registers are set (ST 84). Consequently, the corresponding bit lines become activated.
Then, the write data generating unit provides a word line drive pulse generation circuit with word line drive pulse data corresponding to the data “11” (ST 85). Then, in output of the word line drive pulses, a predetermined number of the pulses are supplied from the word line drive pulse generation circuit to the word lines (ST 86). When the word line drive pulse output is applied to the corresponding word lines only for the predetermined number of pulses, writing of the data “11” to the memory cells ends. The index counter is incremented by 1 (ST 87), and the incremented index value i is checked (ST 88). If the index value i is greater than 4, writing of the four types of data values (“00”, “01”, “10” and “11) to the memory cells has not yet ended. In that case, writing of a next data value (for instance, “10”) is performed. On the one hand, if the index value i is 5, writing of the four types of data values (“00”, “01”, “10”, and “11”) has ended (see, for example, Japanese Laid-Open Patent Publication No. 9-45094).
However, if the erasure action is performed in ETOX type flash memories described above, the program-back-verify action is performed for the memory cells from which information has been excessively erased after collective erasure so that the threshold voltage of memory cells may belong to a distribution range corresponding to a specific data value, to ensure that there will be no memory cell from which information has been excessively erased and that there will be no memory cell to which information has been excessively programmed back. Thus, the program-back time (sum of time during which program-back voltage is applied and the program-back-verify time) is needed.
In addition, in a method of writing information of a four-valued flash memory, writing of four types data values, including program-back by means of the erasure action, is performed. However, as memory cells become smaller with recent miniaturization, due to variation in threshold voltage of selected memory cells that are a target of writing, variation of threshold voltage of adjacent memory cells that are not a target of writing has also increased. FIG. 9 shows a graph illustrating one example of a relationship between the variation in the threshold voltage of the selected memory cells and the variation in the threshold voltage of the adjacent memory cells. Hence, when writing of information has already completed in memory cells adjacent to the selected memory cells to be written, the threshold voltage of the adjacent memory cells also vary due to the variation in the threshold of the selected memory cells, thus possibly causing a readout error when information of the adjacent memory cells is read out.